SECTION Ⅰ Semiconductor Physics and Devices Chapter 1 Semiconductor physics foundation 1.1 Semiconductor materials 1.2 Semiconductor structure 1.3 Semiconductor defects 1.4 Energy band of semiconductor 1.5 Fermi level 1.6 Carrier concentration of semiconductor 1.7 Carrier motion of semiconductor 1.7.1 Carrier drift 1.7.2 Carrier diffusion 1.7.3 Carrier recombination Exercises References Chapter 2 Diode 2.1 Basic structure of diode 2.2 Formation of pn junction and impurity distribution 2.3 Equilibrium pn junction 2.3.1 Formation of space charge region 2.3.2 Energy band of pn junction 2.3.3 Contact potential difference 2.3.4 Space charge region characteristics 2.3.5 Electric field and width of space charge region 2.4 Bias characteristics of diodes 2.4.1 Forward bias 2.4.2 Reverse bias 2.5 Influencing factors of diode DC characteristics 2.5.1 Recombination current and generation current in space charge region 2.5.2 Surface effect 2.5.3 Series resistance effect 2.5.4 Large injection effect 2.5.5 Temperature effect 2.6 Breakdown characteristics of diode 2.6.1 Avalanche breakdown 2.6.2 Tunnel breakdown 2.6.3 Thermoelectric breakdown 2.7 Switching characteristics of diode Exercises References Chapter 3 Bipolar junction transistor 3.1 Introduction of BJT 3.2 Basic architecture of bipolar transistor 3.2.1 Alloy transistor 3.2.2 Alloy diffusion transistor 3.2.3 Planar transistor 3.2.4 Mesa transistor 3.3 Amplification of bipolar junction transistor 3.3.1 Carrier transmisson characteristics 3.3.2 Current amplification coefficient 3.3.3 Amplification conditions
3.4 Characteristic curve of bipolar transistor 3.4.1 Common base characteristic curve 3.4.2 Common emitter characteristic curve 3.5 Reverse current and breakdown voltage characteristics 3.5.1 Reverse current 3.5.2 Breakdown voltage 3.6 Base resistance 3.6.1 Concept of base resistance 3.6.2 Base resistance of comb transistor 3.6.3 Base resistance of circular transistor 3.7 Switching characteristics of bipolar junction transistor 3.7.1 On state and off state 3.7.2 Transient switching characteristics Exercises References Chapter 4 MOS field effect transistor 4.1 Basic structure, principle and classification of MOSFET 4.1.1 Basic structure of MOSFET 4.1.2 Operating principle of MOSFET 4.1.3 Classification of MOSFET 4.2 Threshold voltage of MOSFET 4.2.1 Charge distribution in MOS structure 4.2.2 Threshold voltage of ideal MOSFET 4.2.3 Threshold voltage of actual MOSFET 4.3 DC characteristics of MOSFET 4.3.1 Operating characteristics of MOSFET 4.3.2 Breakdown characteristics of MOSFET 4.4 Small signal parameters and frequency characteristics of MOSFET 4.4.1 Small signal parameters of MOSFET 4.4.2 Frequency characteristics of MOSFET 4.5 Second?order effects of MOSFET 4.5.1 Non?constant mobility effect 4.5.2 Bulk charge effect 4.5.3 Short channel effect 4.5.4 Narrow channel effect 4.6 Switching characteristics of MOSFET 4.6.1 Transient switching delay 4.6.2 Calculation of switching time Exercises References Chapter 5 Power MOSFET 5.1 Introduction 5.2 Structure of power MOSFET devices 5.3 Channel characteristics 5.4 Conduction loss 5.5 Switching characteristics 5.6 Selection of power MOSFET devices Exercises References Chapter 6 Thyristor
6.1 Introduction 6.2 Device structure and working principle 6.3 I?V characteristics of thyristor 6.3.1 Static characteristics 6.3.2 Dynamic characteristics 6.4 Conduction characteristics 6.5 Shutdown characteristics 6.5.1 Interrupt anode current 6.5.2 Reverse voltage interruption Exercises References Chapter 7 IGBT 7.1 Introduction 7.2 Device structure and working mechanism of IGBT 7.3 I?V characteristics of IGBT 7.4 Switching characteristics of IGBT 7.4.1 Conduction characteristics 7.4.2 Shutdown characteristics Exercises References Chapter 8 Passive devices 8.1 Introduction 8.2 Embedded passive devices 8.3 Integrated passive devices 8.4 Integrated resistance 8.4.1 Bipolar transistor processing resistance 8.4.2 CMOS processing resistance 8.4.3 Resistance value calculation and common graphics 8.4.4 Resistance parasitic effect 8.5 Integrated capacitance 8.5.1 Type of integrated capacitance 8.5.2 Capacitance parasitic effect 8.6 Integrated inductance 8.6.1 Integrated inductance structure 8.6.2 Inductive parasitic effect Exercises References Chapter 9 SPICE device model 9.1 Introduction 9.2 Diode SPICE model 9.2.1 DC model of diode 9.2.2 Transient model of diode 9.2.3 AC model of diode 9.2.4 Noise model of diode 9.2.5 Temperature effect of diode 9.3 SPICE model of bipolar transistor 9.3.1 Small signal model of bipolar transistor 9.3.2 Transient analysis 9.3.3 Noise analysis 9.3.4 Temperature effect
9.4 SPICE model of MOS field effect transistor 9.4.1 Small signal model of MOSFET 9.4.2 Noise model of MOSFET 9.4.3 Transient model of MOSFET 9.4.4 Temperature effect of MOSFET 9.4.5 Second order effect and higher order effect models 9.5 SPICE model of passive devices 9.5.1 Resistance 9.5.2 Capacitance 9.5.3 Inductance Exercises References SECTION Ⅱ Semiconductor Manufacturing Process Chapter 10 Semiconductor process technology 10.1 Substrate cleaning 10.1.1 Wet chemical cleaning 10.1.2 Dry cleaning 10.1.3 Beam cleaning 10.2 Oxidation technology 10.2.1 Structure and properties of SiO2 film 10.2.2 Thermal oxidation 10.2.3 Quality analysis of oxide layer 10.2.4 Other oxidation methods 10.3 Graphic processing technology 10.3.1 Photo etching process flow 10.3.2 Photoresist classification 10.3.3 Mask preparation 10.3.4 Photolithography technology 10.3.5 Etching technology 10.3.6 Defect analysis 10.4 Doping technology 10.4.1 Basic concept of doping 10.4.2 Thermal diffusion 10.4.3 Ion implantation 10.4.4 Other doping methods Exercises References Chapter 11 Semiconductor process simulation 11.1 Introduction 11.1.1 Program startup 11.1.2 Example loading 11.2 n?channel MOSFET simulation 11.2.1 Simulation grid construction 11.2.2 Substrate initialization 11.2.3 ATHENA operation and drawing 11.2.4 Gate oxidation process 11.2.5 Ion implantation 11.2.6 Polysilicon gate deposition 11.2.7 Polysilicon etching 11.2.8 Polysilicon oxidation
11.2.9 Polysilicon doping 11.2.10 Isolated oxide deposition 11.2.11 Isolation oxide etching 11.2.12 Source/Drain injection and annealing 11.2.13 Metal deposition 11.2.14 Extraction of device parameters 11.2.15 Half n?channel MOS structure image 11.2.16 Electrode marking 11.2.17 Save ATHENA structure file 11.3 Lithography process simulation 11.3.1 Mask design 11.3.2 Light source selection 11.3.3 Parameter configuration of projection system 11.3.4 Filter parameter configuration 11.3.5 Imaging 11.3.6 Exposure 11.3.7 Baking 11.3.8 Development 11.3.9 Complete lithography process Exercises References Chapter 12 Film preparation technology 12.1 Physical preparation technology 12.1.1 Vacuum foundation 12.1.2 Vacuum evaporation coating 12.1.3 Sputtering coating 12.1.4 Molecular beam epitaxy 12.1.5 Pulsed laser deposition 12.2 Chemical preparation technology 12.2.1 Chemical vapor deposition 12.2.2 Chemical solution preparation 12.2.3 Soft solution processing Exercises References SECTION Ⅲ Semiconductor Packaging, Testing and Simulating Chapter 13 Semiconductor packaging technology 13.1 Introduction 13.2 Packaging function 13.2.1 Physical protection 13.2.2 Electrical connection 13.2.3 Heat dissipation 13.3 Packaging process 13.3.1 Overview of process flow 13.3.2 Chip mounting 13.3.3 Chip interconnection 13.3.4 Molding technology 13.4 Packaging materials 13.4.1 Molding materials 13.4.2 Frame materials 13.5 Packaging type
13.5.1 Pin 13.5.2 Surface Mount 13.5.3 Array 13.6 Other packaging technologies 13.6.1 Multi?chip packaging 13.6.2 Chip level packaging 13.6.3 Pre?encapsulated interconnection system 13.6.4 Flip chip packaging Exercises References Chapter 14 Semiconductor parameter testing technology 14.1 Semiconductor resistivity testing 14.1.1 Introduction 14.1.2 Four?point probe testing method 14.1.3 Influencing factors 14.2 Conductivity type testing of semiconductor 14.2.1 Hot and cold probe method 14.2.2 Single probe point contact rectification method 14.2.3 Influencing factors 14.3 Oxide film thickness testing 14.3.1 Color contrast method 14.3.2 Optical interferometry 14.3.3 High frequency turbulence method 14.3.4 Ellipsometry 14.4 Junction depth testing 14.5 Testing of impurity concentration of epitaxial layer 14.6 Testing of non?equilibrium minority carrier lifetime 14.6.1 Overview 14.6.2 Lifetime of non?equilibrium minority carriers 14.6.3 Testing method 14.7 Bipolar transistor parameter testing 14.7.1 DC parameter testing 14.7.2 Testing of Ccr′bb product 14.7.3 Testing of switching parameters 14.7.4 Characteristic frequency testing 14.7.5 Steady?state thermal resistance testing 14.8 MOSFET parameter testing 14.8.1 DC characteristic testing 14.8.2 Testing of input capacitance and feedback capacitance 14.8.3 Testing of power gain and noise coefficient Exercises References Chapter 15 Realization technology of semiconductor device characteristic simulation based on GUI 15.1 Introduction 15.2 Software architecture design 15.3 Project creation 15.4 Main page design 15.5 Semiconductor physical parameters 15.5.1 Fermi potential calculation 15.5.2 Carrier concentration calculation
15.5.3 Energy level calculation of single hydrogen atom 15.6 Semiconductor device parameters 15.6.1 CMOS device characteristics 15.6.2 Resistivity calculation 15.6.3 Junction depth calculation 15.6.4 Calculation of oxide film thickness 15.6.5 Contact potential difference calculation 15.7 Multimedia resources 15.8 Accessibility functions 15.9 Help file design Exercises References Appendix Keys to exercises
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