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大數據分析(數據倉庫項目實戰)

  • 作者：編者:尚矽谷IT教育|責編:李冰
  • 出版社：電子工業
  • ISBN：9787121396007
  • 出版日期：2020/11/01
  • 裝幀：平裝
  • 頁數：386
人民幣：RMB 100 元      售價：元
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內容大鋼
    本書是一本系統介紹數字電路設計的優秀教材，旨在教會讀者關於數字設計的基本概念和基本方法，並在其前一版的基礎上進行了全面的修訂與更新。全書共10章，內容涉及數字邏輯的基本理論，組合邏輯電路，時序邏輯電路，寄存器和計數器，存儲器與可編程邏輯器件，寄存器傳輸級設計，半導體和CMOS集成電路，標準IC和FPGA實驗，標準圖形符號，Verilog HDL、VHDL、System Verilog與數字系統設計等。全書結構嚴謹，選材新穎，內容深入淺出，緊密聯繫實際，教輔資料齊全。
    本書可作為電氣工程、電子工程、通信工程、電腦工程和電腦科學與技術等相關專業的雙語教材，也可作為電子設計工程師的參考書。
作者介紹
編者:尚矽谷IT教育|責編:李冰
目錄
1 Digit a l S ys tems and Binar y Numbers
  1.1  Digital Systems
  1.2  Binary Numbers
  1.3  Number-Base Conversions
  1.4  Octal and Hexadecimal Numbers
  1.5  Complements of Numbers
  1.6  Signed Binary Numbers
  1.7  Binary Codes
  1.8  Binary Storage and Registers
  1.9  Binary Logic
2 Boolean Algebra and Logic Gate s
  2.1  Introduction
  2.2  Basic Definitions
  2.3  Aomatic Definition of Boolean Algebra
  2.4  Basic Theorems and Properties of Boolean Algebra
  2.5  Boolean Functions
  2.6  Canonical and Standard Forms
  2.7  Other Logic Operations
  2.8  Digital Logic Gates
  2.9  Integrated Circuits
3 Gate-Level Minimization
  3.1  Introduction
  3.2  The Map Method
  3.3  Four-Variable K-Map
  3.4  Product-of-Sums Simplification
  3.5  Don』t-Care Conditions
  3.6  NAND and NOR Implementation
  3.7  Other Two-Level Implementations
  3.8  Exclusive-OR Function
  3.9  Hardware Description Languages (HDLs)
  3.10  Truth Tables in HDLs
4 Combinational Logic
  4.1  Introduction
  4.2  Combinational Circuits
  4.3  Analysis of Combinational Circuits
  4.4  Design Procedure
  4.5  Binary Adder–Subtractor
  4.6  Decimal Adder
  4.7  Binary ltiplier
  4.8  Magnitude Comparator
  4.9  Decoders
  4.10  Encoders
  4.11  ltiplexers
  4.12  HDL Models of Combinational Circuits
  4.13  Behavioral Modeling
  4.14  Writing a Simple Testbench
  4.15  Logic Silation
5 Synchronous Sequential Logic
  5.1  Introduction
  5.2  Sequential Circuits

  5.3  Storage Elements: Latches
  5.4  Storage Elements: Flip-Flops
  5.5  Analysis of Clocked Sequential Circuits
  5.6  Synthesizable HDL Models of Sequential Circuits
  5.7  State Reduction and Assignment
  5.8  Design Procedure
6 Registers and Counters
  6.1  Registers
  6.2  Shift Registers
  6.3  Ripple Counters
Synchronous Counters
  6.5  Other Counters
  6.6  HDL Models of Registers and Counters
7 Memory and Programmable Logic
  7.1  Introduction
  7.2  Random-Access Memory
  7.3  Memory Decoding
  7.4  Error Detection and Correction
  7.5  Read-Only Memory
  7.6  Programmable Logic Array
  7.7  Programmable Array Logic
  7.8  Sequential Programmable Devices
8 Design at the Registe r Transfer Leve l
  8.1  Introduction
  8.2  Register Transfer Level (RTL) Notation
  8.3  RTL Descriptions
  8.4  Algorithmic State Machines (ASMs)
  8.5  Design Example (ASMD CHART)
  8.6  HDL Description of Design Example
  8.7  Sequential Binary ltiplier
  8.8  Control Logic
  8.9  HDL Description of Binary ltiplier
  8.10  Design with ltiplexers
  8.11  Race-Free Design (Software Race Conditions)
  8.12  Latch-Free Design (Why Waste Silicon?)
  8.13  SystemVerilog—An Introduction
9 Laborator y Experiments with
Standard ICs and FPGAs
  9.1  Introduction to Experiments
  9.2  Experiment 1: Binary and Decimal Numbers
  9.3  Experiment 2: Digital Logic Gates
  9.4  Experiment 3: Simplification of Boolean Functions
  9.5  Experiment 4: Combinational Circuits
  9.6  Experiment 5: Code Converters
  9.7  Experiment 6: Design with ltiplexers
  9.8  Experiment 7: Adders and Subtractors
  9.9  Experiment 8: Flip-Flops
  9.10  Experiment 9: Sequential Circuits
  9.11  Experiment 10: Counters
  9.12  Experiment 11: Shift Registers

  9.13  Experiment 12: Serial Addition
  9.14  Experiment 13: Memory Unit
  9.15  Experiment 14: Lamp Handball
  9.16  Experiment 15: Clock-Pulse Generator
  9.17  Experiment 16: Parallel Adder and Acculator
  9.18  Experiment 17: Binary ltiplier
  9.19  HDL Silation Experiments and Rapid Prototyping with FPGAs
10 Standard Graphic Symbols
  10.1  Rectangular-Shape Symbols
  10.2  Qualifying Symbols
  10.3  Dependency Notation
  10.4  Symbols for Combinational Elements
  10.5  Symbols for Flip-Flops
  10.6  Symbols for Registers
  10.7  Symbols for Counters
  10.8  Symbol for RAM
Appendix
Answers to Selected Problems

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